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3C509 and 3C509-TP Adapters Technical Reference Guide ------------------------------------------------------------------- For 3Com User Group Information 1-800-NET-3Com or your local 3Com office Manual Part No. 8369-00 Published March 1992. (C) Copyright 3Com Corporation, 1992. All rights reserved. No part of this manual may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without permission from 3Com Corporation. 3Com Corporation reserves the right to revise this publication and to make changes in content from time to time without obligation on the part of 3Com Corporation to provide notification of such revision or change. 3Com Corporation provides this guide without warranty of any kind, either implied or expressed, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. 3Com may make improvements or changes in the product(s) and/or the program(s) described in this manual at any time. Use, duplication, or disclosure by the government shall be expressly subject to restrictions as set forth in subparagraph (c) (1) (ii) for restricted Rights in Technical Data and Computer Software clause at 252.227-7013 of the DOD FAR Supp. Ask3Com and CardBoard are service marks of 3Com Corporation. 3Com and EtherLink are registered trademarks and EtherLink III is a trademark of 3Com Corporation. IBM and Personal Computer AT are registered trademarks of International Business Machines Corporation. 3Com 3C509 and 3C509-TP Technical Reference Guide ii Contents Chapter 1 Introduction Chapter 2 Architectural Overview Chapter 3 Data Structures FIFO .........................................................3-1 Receive Packet Structure ..................................3-1 Transmit Packet Structure .................................3-1 Chapter 4 Description of Operation Receive ......................................................4-1 Receive Packet and RX Status ..............................4-1 Receive Early .............................................4-1 Receive Complete ..........................................4-2 Transmit .....................................................4-2 Transmit Packet and Transmit Completion ...................4-2 Transmitting a Packet .....................................4-2 Transmit Underrun .........................................4-3 Chapter 5 Window Set Window 0 Registers - Setup ...................................5-1 Window 1 Registers - Operating Set ...........................5-2 Window 2 Registers - Station Address Setup/Read ..............5-2 Window 3 Registers - FIFO Management .........................5-3 Window 4 Registers - Diagnostics .............................5-3 Window 5 Registers - Command Results and Internal State ......5-4 Window 6 Registers - Statistics ..............................5-5 Chapter 6 Register Definition Command Register .............................................6-1 Status Register ..............................................6-7 FIFO Registers ...............................................6-9 RX Status .................................................6-9 TX Status .................................................6-11 RX PIO Data Read ..........................................6-12 TX PIO Data Write .........................................6-12 Free Receive Bytes ........................................6-13 Free Transmit Bytes .......................................6-13 Timer Register ...............................................6-13 Statistics Registers .........................................6-14 Statistics ................................................6-14 Diagnostic Registers .........................................6-16 Media Type and Status .....................................6-16 Net Diagnostic Port .......................................6-16 FIFO Diagnostic Port ......................................6-17 Host Diagnostic Port ......................................6-18 TX Diagnostic Port ........................................6-19 Ethernet Controller Status ................................6-19 Chapter 7 Adapter Configuration and Enable Automatic Configuration at Power on Reset ....................7-1 ISA Activation Mechanism .....................................7-1 EISA Activation Mechanism ....................................7-3 Window 0 Register Set ........................................7-4 Manufacturer Code Register (Read Only - Offset 0) .........7-4 Product ID Register (Read Only - Offset 2) ................7-4 Configuration Control Register (Read/Write - Offset 4) ....7-4 Address Configuration Register (Read/Write - Offset 6) ....7-5 3Com 3C509 and 3C509-TP Technical Reference Guide iii Resource Configuration Register (Read/Write - Offset 8) ...7-6 EEPROM Command Register (Read/Write - Offset A) ...........7-6 EEPROM Data Register (Read/Write - Offset C) ..............7-7 Command Register (Read/Write - Offset E) ..................7-7 Test Mode and "Bad" Configuration Recovery ...................7-7 EEPROM Data Structure ........................................7-8 Chapter 8 ISA/EISA Bus Interface Supported Slot Times and Cycle Types .........................8-1 16-bit ISA Slot ...........................................8-1 EISA Slot .................................................8-1 DC Characteristics - Pin Drive/Load Types ....................8-1 Board Edge Connector Pins ....................................8-1 Chapter 9 External Configuration Options Boundary Scan Configuration ..................................9-1 Forced Configuration .........................................9-1 Physical Layer Configuration .................................9-1 Physical Layer Test Access ...................................9-2 3Com 3C509 and 3C509-TP Technical Reference Guide iv Figures 2-1. Block Diagrams ..........................................2-2 3-1. Receive Packet Structure ................................3-1 3-2. Transmit Packet Structure ...............................3-2 5-1. Setup ...................................................5-1 5-2. Operating Set ...........................................5-2 5-3. Station Address Setup/Read ..............................5-2 5-4. FIFO Management .........................................5-3 5-5. Diagnostics .............................................5-3 5-6. Command Results and Internal State ......................5-4 5-7. Statistics Maintained by the Adapter ....................5-5 7-1. ID Sequence State Machine (IDS) .........................7-1 3Com 3C509 and 3C509-TP Technical Reference Guide v Chapter 1 Introduction The purpose of this document is to describe the basic architecture of the EtherLink III (tm) Parallel Tasking 16-bit Coax adapter (3C509) and the Parallel Tasking 16-bit 10BASE-T adapter (3C509-TP), and to serve as a reference for software and test engineers. Aspects of the architecture have patents pending. These adapters are part of the new EtherLink III family of high- performance 16-bit adapters. These two members of the family interface with the ISA bus (coax and 10BASE-T). The 3C509 adapter includes BNC and AUI connectors, and the 3C509-TP adapter includes RJ-45 and AUI connectors. These adapters are software-compatible with each other, but not with any other 3Com (R) adapter. This manual describes both ISA bus versions. NOTE: Unless otherwise stated, the name "3C509 adapter" refers to both the 3C509 and the 3C509-TP adapters. Highlights of the 3C509 adapter include: - The 3Com-designed Ethernet controller, encoder/decoder, 10BASE-T transceiver, host interface, and packet buffer all integrated into one ASIC. - The packet buffer size is 4 K. - The majority of the components are surface mount. - The printed circuit board (PCB) is two layers. - High performance in client applications. - 16-bit data path to/from the ISA bus. NOTE: The 3C509 adapter is optimized to perform best in a client with processors such as the 80286-6 MHz and above. 3Com 3C509 and 3C509-TP Technical Reference Guide 1-1 Chapter 2 Architectural Overview The 3C509 and 3C509-TP 16-bit adapters are designed to be efficient, low-latency network adapters optimized for client environments. The emphasis on low latency in the design process has resulted in an adapter with only 4 K of buffer space on board, which appears as two dedicated 2K FIFOs to the host. Aspects of the architecture have patents pending. The network transceiver consists of a dedicated receiver and a dedicated transmitter, allowing loopback operation at full network bandwidth. At the 10BASE-T interface, automatic polarity reversal and hardware link beat LED indication are supported. At the register level, support is provided for critical network management functions as well as supplementary 10BASE-T functions. An integrated encoder/decoder and 10BASE-T transceiver improve reliability while reducing the cost of the system. The EEPROM sets all configuration options on the board, eliminating the need for jumpers. Methods for EISA auto configuration are supported. Board type and revision number are electronically readable. Interrupt level, I/O base address, and the decode address of the optional remote boot PROM are among the configuration options. A key provides security against accidental reconfiguration. To facilitate a variety of platforms and operating systems, programmed I/O (PIO) is the only method of data transfer supported. The 4K RAM is configured as two 2K FIFOs: one for transmit and one for receive. Various early indication/early start mechanisms are incorporated to improve performance and make operation within 2K possible while minimizing the likelihood of overruns or underruns. Interrupts can be programmed to signal the CPU under various early indication conditions, and timer mechanisms are incorporated to allow measurement of system latencies. These features reduce latency and minimize host intervention in platforms where this is appropriate. A high-level command interface provides for setting early indications and managing the adapter while using only 16 bytes of I/O space. See Figure 2-1 for block diagrams of the 3C509 (coaxial) and 3C509-TP (twisted-pair) adapters. 3Com 3C509 and 3C509-TP Technical Reference Guide 2-1 Twisted-pair Adapter (3C509-TP) +--------+ | EEPROM | +---^----+ | ........|............................................................. . | +----------+ +------------+ . . | | 512 x 32 | | Network | . . | | RAM FIFO | | Management | . . | +-----^----+ +------------+ . . | | +------------------+ . P . | +----v----+ | | +-------+ +-------+ . h H. +-----v-----+ | FIFO <-> Transmit Control <-> <-> AUI <-->y o. | <->Transmit | | | | | +-------+ . s s. | | +---------+ +-^------^-------^-+ |Encoder| . i t. | | | | | | | . c . | | | +----v-----+ | | | +-------+ . a B. | Host | | | Ethernet | | |.......| |Twisted| . l u. | Interface | | |Controller| | | | | Pair <--> s. | | | +----^-----+ | | <-> Xcvr | . M <-> | | | | | | | | . e . | | +---------+ +-v------v-------v-+ |Decoder| +-------+ . d . | <-> FIFO | | | | | . i . +-----^-----+ | Receive <-> Receive Control <-> | . a . | +----^----+ | | +---^---+ . . | | +------------------+ | . . | +-----v----+ +--------+ | . . | | 512 x 32 | | Clocks | | . . | | RAM FIFO | +--------+ | . . | +----------+ | ASIC . ........|............................................|................ | | +-----v-----+ +--v--+ | Boot PROM | | VCO | +-----------+ +-----+ Figure 2-1. Block Diagrams (1 of 2) 3Com 3C509 and 3C509-TP Technical Reference Guide 2-2 Coaxial Adapter (3C509) +--------+ | EEPROM | +---^----+ | ........|............................................................. . | +----------+ +------------+ . . | | 512 x 32 | | Network | . . | | RAM FIFO | | Management | . . | +-----^----+ +------------+ . . | | +------------------+ . P . | +----v----+ | | +-------+ +-------+ . h H. +-----v-----+ | FIFO <-> Transmit Control <-> <-> AUI <-->y o. | <->Transmit | | | | | +-------+ . s s. | | +---------+ +-^------^-------^-+ |Encoder| ........... i t. | | | | | | | . c . | | | +----v-----+ | | | .+-------+ a B. | Host | | | Ethernet | | |.......| .| | l u. | Interface | | |Controller| | | | .|Coaxial<-> s. | | | +----^-----+ | | <--> Xcvr | M <-> | | | | | | .| | e . | | +---------+ +-v------v-------v-+ |Decoder| .+-------+ d . | <-> FIFO | | | | | . i . +-----^-----+ | Receive <-> Receive Control <-> | . a . | +----^----+ | | +---^---+ . . | | +------------------+ | . . | +-----v----+ +--------+ | . . | | 512 x 32 | | Clocks | | . . | | RAM FIFO | +--------+ | . . | +----------+ ASIC | . ........|............................................|...... | | +-----v-----+ +--v--+ | Boot PROM | | VCO | +-----------+ +-----+ Figure 2-1. Block Diagrams (2 of 2) 3Com 3C509 and 3C509-TP Technical Reference Guide 2-3 Chapter 3 Data Structures The following sections describe the data structures used for the adapter's FIFO. 3.1 FIFO The adapter's 4 K SRAM is organized into two 512 x 32 FIFOs: one for transmit and one for receive. The size, alignment, and padding of the packet stored in SRAM are set to double word boundaries. The amount of unused space is monitored in the free byte registers: Free Transmit Bytes and Free Receive Bytes. 3.1.1 Receive Packet Structure Figure 3-1 shows a model of the receive packet structure as it is stored in the FIFO. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | | 60 - 1514 bytes of packet data | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Padding to double word | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Undefined | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Figure 3-1. Receive Packet Structure - Packet data is contained in the first 60 to 1,514 bytes. - Padding to a double word (dword) boundary follows. - There may be additional overhead bytes associated with each packet that are used by the hardware but must not be read by the host. The receive status information is in the RX Status register. Software must not read past the end of the packet (the software can read padding to a dword boundary). To progress to the next packet, the software must issue an RX Discard command that discards the remainder of the packet, if any, and pops the current RX Status, replacing it with the next packet status, if any. 3.1.2 Transmit Packet Structure Figure 3-2 shows a model of the transmit packet structure as it is stored in the FIFO. 3Com 3C509 and 3C509-TP Technical Reference Guide 3-1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |INT| Unassigned | Length | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Unassigned | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | | | 14 - 1514 bytes of packet data | | | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Padding to double word | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Figure 3-2. Transmit Packet Structure - The preamble is two words long. The first word contains the length of the packet in bytes and the Interrupt (Int) on successful Transmit Complete bit in Bit 15. This bit is maskable in the Interrupt Mask register. The second word is reserved. - Packet data follows next 14 to 1,514 bytes. - Padding to a double word boundary is last. The packet length is measured in bytes. If a packet length is not a multiple of four, pad bytes must be added to bring the packet size in the FIFO to a 4-byte boundary. The packet length, however, must reflect the true size of the packet (before the padding). The hardware automatically pads packets shorter than 60 bytes. 3Com 3C509 and 3C509-TP Technical Reference Guide 3-2 Chapter 4 Description of Operation The data transfer mode for the 3C509 adapter is programmed I/O (PIO). As data is received off the wire, it accumulates in the receive FIFO. The driver reads the data off the adapter a byte or a word at a time through the PIO Data Read register. Similarly, transmit data can be written to the adapter a byte or a word at a time, and it accumulates in the transmit (TX) FIFO. Once a packet has been transmitted out of the TX FIFO, it is discarded and the space it consumes is available. The transmit and receive configurations are described below. 4.1 Receive 4.1.1 Receive Packet and RX Status Each packet in the RX FIFO consists of the packet data, padded to a dword boundary. The RX Status register always maintains the status of the packet at the head of the FIFO. After using PIO to read the data, the host must issue an RX Discard command to update the RX Status register for the next packet. The driver may transfer all of the receive data from the FIFO via PIO. The driver can take interrupts when RX Early threshold bytes of a packet have been received, or when an entire packet has been received. The driver can determine the size of the packet (number of bytes remaining/received so far) at the head of the RX FIFO by reading the RX Status register. Once the packet has been completely received, any errors that occurred during reception are posted in the RX Status register. 4.1.2 Receive Early The RX Early interrupt will probably be enabled only if the protocol interface allows for early receive indications. However, it is possible for the driver to take the RX Early interrupt in order to compute the packet size (perhaps only for 802.3 packets) and generate the equivalent of an early RX Complete indication. The driver may choose to set the RX Early threshold to slightly less than the protocol's early lookahead size to overlap the reception of the final bytes with the interrupt latency. On entry to the interrupt handler, the RX Status register can be examined to see whether the threshold needs to be adjusted. Once RX Early has been set, the driver has only to acknowledge the interrupt and it will not become active again (unless reprogrammed higher) until RX Status is updated for the next packet. The driver must transfer the data from the RX FIFO via PIO into a dedicated lookahead area to make the data accessable to the protocol stack. 3Com 3C509 and 3C509-TP Technical Reference Guide 4-1 4.1.3 Receive Complete If an RX Early indication had been given for the packet, then the lookahead bytes have already been read in. Otherwise, they must be read in now, using PIO to transfer them to the dedicated lookahead area to make the data addressable to the protocol stack. Once a scatter descriptor is available from the protocol, the data must be copied out of the lookahead area and the RX FIFO. 4.2 Transmit PIO is the only mode of operation supported for transmit. This mode is discussed in more detail below. 4.2.1 Transmit Packet and Transmit Completion Each packet in the TX FIFO consists of a transmit preamble followed by the transmit data padded to a dword boundary. The transmit preamble consists of two words. The first word specifies the length of the packet in bytes, and whether or not to generate an interrupt when the packet is transmitted successfully. The second word is unassigned. The packet length is the actual number of bytes in the FIFO to be sent to the wire, excluding any padding to double words. If the packet is less than the minimum length (60 bytes not including CRC), it need not be padded by the software. Instead, the 3C509 adapter will pad the packet to the minimum length before giving it to the Ethernet controller. The driver will request an interrupt on successful transmit completion only if the protocol has requested a confirmation. The driver must queue up such requests to retrieve the protocol handle for the transmit confirmation. When any Transmit Complete interrupt comes in, the driver examines the TX Status register. This completion is for the head of the queue if the interrupt requested bit is set in TX Status, since transmits complete in order. The driver must serialize this process to guarantee that it works properly. If an error occurs while the packet is being transmitted, the adapter always generates an interrupt and disables the transmitter. If the host determines from TX Status that the confirmation is not for a queued request, it can use the error information to update its statistics counters. In any case, the host must manually restart the transmitter by issuing the TX Enable command once it has emptied the TX Status stack as the result of an error. 4.2.2 Transmitting a Packet All data to be transmitted must be moved into the FIFO by the driver. Multiple packets can be moved into the FIFO as long as the host is prepared to deal with running out of TX FIFO space. Typically the driver will copy as much of the packet to the adapter as possible. If one or more packets precede this one in the FIFO, then the FIFO can run out of space. If this happens, the driver can issue the TX Available command to request an interrupt once there is sufficient space for the rest of the packet. 3Com 3C509 and 3C509-TP Technical Reference Guide 4-2 The Set TX Available Threshold command causes the adapter to generate an interrupt when the specified number of bytes is available in the TX FIFO. This allows the driver to return and continue copying the data later, when some of the data in the TX FIFO has been transmitted. When TX Available is used, the possibility of an underrun always exists if the interrupt latency is high enough (for example, 1 ms on a window switch under OS/2). If underruns are a problem, they can be avoided by reprogramming the TX Start threshold to be greater than the number of bytes transferred to that point. That way the driver can guarantee that the packet will not start transmitting before the TX Available interrupt is serviced. The driver can be written so that it makes this adjustment only when the amount of the packet copied to the FIFO is small enough for concern (that is, less than the number of bytes that can be transmitted within the measured interrupt latency), or the driver can make the adjustment semipermanently (reset on some timer tick multiple) whenever an underrun occurs. When a packet is currently being copied to the FIFO and the protocol issues another transmit request, the driver will have to queue the gather descriptor. However, this queue - the awaiting download queue - is different from the transmit completion queue described above. The awaiting download queue is emptied and the queue entries released by copying the data to the adapter. 4.2.3 Transmit Underrun When the transmit FIFO underruns, the 3C509 adapter will generate a bad CRC for the packet. A Transmit Complete interrupt will be generated to the driver, specifying a transmit underrun error. When the driver detects this error, it must first issue a TX Reset command before using TX Enable to reenable the transmitter. Whenever the driver encounters an underrun, it takes special care to guarantee that the next transmit packet does not underrun by setting the TX Start threshold large enough so that it does not start until the packet is completely copied to the adapter. For subsequent packets, the driver reacts quickly to changes in the operating environment by adjusting the TX Start threshold according to new information on interrupt latencies, and other system performance measurements. The exact mechanism used is beyond the scope of this document. NOTE: Underruns occur only when the packet is being copied to the adapter. Therefore, the driver should be able to retransmit the packet. Checking for underruns and retransmissions can greatly reduce the performance impact of an underrun (to the point that an occasional underrun is acceptable). 3Com 3C509 and 3C509-TP Technical Reference Guide 4-3 Chapter 5 Window Set The 3C509 adapter register set consists of several 8-word register windows. The windows are numbered, and each window presents a different register set to the host through the standard 16-byte I/O space of the adapter. At power-up, or after a Global Reset, Window 0 is the working register set. Window 0 contains setup information, including the registers reflecting the EEPROM setup information. Window 1 contains the standard register set. This includes all of the registers used on the driver critical path. Accessing other windows will require switching away and back in a critical section. The driver will switch to Window 1 during initialization and assume that this set is always current from that point on. Other windows contain the statistics information, report the adapter state, allow for reconfiguration, and support various diagnostics. 5.1 Window 0 Registers - Setup This window contains configuration registers, including EISA setup and EEPROM access. Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-----+-------------------------+ 0C | EEPROM Data | | EEPROM Data | +-------------------------------+ +-------------------------------+ 0A | EEPROM Command | | EEPROM Command | +-------------------------------+ +-------------------------------+ 08 | Resource Configuration | | Resource Configuration | +-------------------------------+ +-------------------------------+ 06 | Address Configuration | | Address Configuration | +-------------------------------+ +-------------------------------+ 04 | Configuration Control | | Configuration Control | +-------------------------------+ +-------------------------------+ 02 | Adapter ID | | Adapter ID | +-------------------------------+ +-------------------------------+ 00 | | | Manufacturer ID | +-------------------------------+ +-------------------------------+ Figure 5-1. Setup 3Com 3C509 and 3C509-TP Technical Reference Guide 5-1 5.2 Window 1 Registers - Operating Set The window set is assumed to be on critical path. The TX Status and Timer registers must be read separately as byte registers. Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-----+-------------------------+ 0C | | | Free Transmit Bytes | +---------------+---------------+ +---------------+---------------+ 0A | TxStatus | | | Tx Status | Timer | +---------------+---------------+ +---------------+---------------+ 08 | | | Rx Status | +-------------------------------+ +-------------------------------+ 06 | | | | +-------------------------------+ +-------------------------------+ 04 | | | | +-------------------------------+ +-------------------------------+ 02 | Tx PIO Data Write | | Rx PIO Data Read | +-------------------------------+ +-------------------------------+ 00 | Tx PIO Data Write | | Rx PIO Data Read | +-------------------------------+ +-------------------------------+ Figure 5-2. Operating Set 5.3 Window 2 Registers - Station Address Setup/Read The station address must be read out of the EEPROM and written using these registers before reception is enabled. Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-----+-------------------------+ 0C | | | | +-------------------------------+ +-------------------------------+ 0A | | | | +-------------------------------+ +-------------------------------+ 08 | | | | +-------------------------------+ +-------------------------------+ 06 | | | | +---------------+---------------+ +---------------+---------------+ 04 | Address 5 | Address 4 | | Address 5 | Address 4 | +---------------+---------------+ +---------------+---------------+ 02 | Address 3 | Address 2 | | Address 3 | Address 2 | +---------------+---------------+ +---------------+---------------+ 00 | Address 1 | Address 0 | | Address 1 | Address 0 | +---------------+---------------+ +---------------+---------------+ Figure 5-3. Station Address Setup/Read 3Com 3C509 and 3C509-TP Technical Reference Guide 5-2 5.4 Window 3 Registers - FIFO Management Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-----+-------------------------+ 0C | | | Free Transmit Bytes | +-------------------------------+ +-------------------------------+ 0A | | | Free Receive Bytes | +-------------------------------+ +-------------------------------+ 08 | | | | +-------------------------------+ +-------------------------------+ 06 | | | | +-------------------------------+ +-------------------------------+ 04 | | | | +-------------------------------+ +-------------------------------+ 02 | | | | +-------------------------------+ +-------------------------------+ 00 | | | | +-------------------------------+ +-------------------------------+ Figure 5-4. FIFO Management 5.5 Window 4 Registers - Diagnostics Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-----+-------------------------+ 0C | | | | +-------------------------------+ +-------------------------------+ 0A | Media Type and Status | | Media Type and Status | +-------------------------------+ +-------------------------------+ 08 | Ethernet Controller Status | | Ethernet Controller Status | +-------------------------------+ +-------------------------------+ 06 | Net Diagnostic | | Net Diagnostic | +-------------------------------+ +-------------------------------+ 04 | FIFO Diagnostic | | FIFO Diagnostic | +-------------------------------+ +-------------------------------+ 02 | Host Diagnostic | | Host Diagnostic | +-------------------------------+ +-------------------------------+ 00 | TX Diagnostic | | TX Diagnostic | +-------------------------------+ +-------------------------------+ Figure 5-5. Diagnostics 3Com 3C509 and 3C509-TP Technical Reference Guide 5-3 5.6 Window 5 Registers - Command Results and Internal State This window contains registers that allow the parameters set by command to be read back for diagnostic purposes. Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-----+-------------------------+ 0C | | | Read Zero Mask | +-------------------------------+ +-------------------------------+ 0A | | | Interrupt Mask | +-------------------------------+ +-------------------------------+ 08 | | | RX Filter (lower 4 bits only) | +-------------------------------+ +-------------------------------+ 06 | | | RX Early Threshold | +-------------------------------+ +-------------------------------+ 04 | | | | +-------------------------------+ +-------------------------------+ 02 | | | TX Available Threshold | +-------------------------------+ +-------------------------------+ 00 | | | TX Start Threshold + 4 | +-------------------------------+ +-------------------------------+ Figure 5-6. Command Results and Internal State 3Com 3C509 and 3C509-TP Technical Reference Guide 5-4 5.7 Window 6 Registers - Statistics Reading a statistic also zeroes it. These registers may be read only while statistics collection has been disabled temporarily. Statistics that are word-sized must be read as words, and those that are bytes must be read as bytes. Writing to these registers is supported for debugging purposes. Refer to "Statistics Registers" in Chapter 6 for more information. Port Indx Write Function Read Function ---- -------------- ------------- 1 1 1 1 1 1 1 1 1 1 1 1 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 +-------------------------------+ +-----+-------------------------+ 0E | Command | | Win | Status | +-------------------------------+ +-------------------------------+ 0C | Total Bytes Transmitted OK | | Total Bytes Transmitted OK | +-------------------------------+ +-------------------------------+ 0A | Total Bytes Received OK | | Total Bytes Received OK | +---------------+---------------+ +---------------+---------------+ 08 | | Xmit Deferrals| | | Xmit Deferrals| +---------------+---------------+ +---------------+---------------+ 06 | Frames Recv OK| Frames Xmit OK| | Frames Recv OK| Frames Xmit OK| +---------------+---------------+ +---------------+---------------+ 04 | Recv Overruns | Late Collision| | Recv Overruns | Late Collision| +---------------+---------------+ +---------------+---------------+ 02 | One Collision | Multiple Coll | | One Collision | Multiple Coll | +---------------+---------------+ +---------------+---------------+ 00 | No SQE Xmits | Carrier Lost | | No SQE Xmits | Carrier Lost | +---------------+---------------+ +---------------+---------------+ Figure 5-7. Statistics Maintained by the Adapter 3Com 3C509 and 3C509-TP Technical Reference Guide 5-5 Chapter 6 Register Definition The following sections describe the function and usage of each of the registers needed in normal operation of the 3C509 adapter. The adapter configuration and enable registers in Window 0 are discussed in Chapter 7. 6.1 Command Register Function: Issues commands to adapter Location: All windows/Port 0E Type: Write only Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Command Code | Command Argument | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 15-11 5-bit code for command to be executed. Bits 10-0 11-bit argument if any. For commands with no arguments, these bits can be set to anything. Many adapter functions are controlled by the Command register. For example, a command is used to switch windows. Commands must be written as a word even if they have no parameters. However, the following is acceptable for commands with no parameters: mov dx, PortCmdStatus mov ah, CMD_X out dx, ax Most commands execute in one I/O cycle except those marked with an asterisk (*). The software must poll the Command-in-Progress bit in the Status register to determine when one of these commands is completed. Since only a single command may be outstanding at any given time, the host must do this in a critical section. The commands are listed below. The 5-bit command code is specified in binary before each command. If the command has an 11-bit argument, it is given in parentheses following the command name in the format aaa aaaa aaaa. Also: - An x signifies a bit in the argument. - A 0 signifies a bit that must be zero. - A z signifies either a 0 or a 1, but will be treated as a 0. - A 1 signifies either a 0 or a 1, but will be treated as a 1. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-1 00000 Global Reset (000 0000 0000) This command has the same effect as a power-up reset. It is implemented with a minimum amount of logic to ensure success. This command requires a significant amount of time to execute since it involves rereading the EEPROM. The timer may not be used for this delay period. The host must wait at least 1 ms after issuing this command before it touches the adapter again. The argument to this command must be all zeros. 00001 Select Register Window (000 0000 0xxx) This command selects register window xxx. The current register window is available in the Status register. After power-up, Window 0 is in effect. 00010 Start Coaxial Transceiver This command affects only the 10BASE2 operation. It starts the DC-DC converter that drives the on-board coaxial Ethernet transceiver. After power-up, the coaxial transceiver must be started manually with this command. The host must delay at least 800 us after issuing this command before using the coaxial transceiver. This can be accomplished by starting the timer and waiting until it pegs at its maximum value of FFh. The host must read the Address Configuration register (refer to "Address Configuration Register" in Chapter 7) from the EEPROM to determine whether to issue this command. 00011 RX Disable This command disables the Ethernet controller receiver. If a packet is in the process of being received, it will be received and the Ethernet controller receiver will be disabled after the packet has been completely received. To enable the receiver, use RX Enable. After power-up, the receiver is in the disabled state. 00100 RX Enable This command enables the Ethernet controller receiver. If a packet is in the process of being transmitted on the wire, it will not be received. To disable the receiver, use RX Disable or RX Reset. After power-up, the receiver is in the disabled state and must be enabled with this command. 00101 RX Reset (000 0000 0000) This command empties the RX FIFO, disables the Ethernet controller, resets the RX Filter and RX Early threshold to defaults, and aborts reception if a packet is currently being received. Do not issue RX Reset unless it is absolutely required. The argument to this command must be all zeros. 01000 RX Discard Top Packet* This command discards the remainder of the top packet in the RX FIFO (the adapter can do this faster than the host). If the packet has been completely received, use the RX Status register to update any statistics before issuing this command. If the packet has not been completely received, the adapter will ignore the remainder of the packet as if the receiver had been disabled, then reenabled. The RX Discard pops the current RX Status and replaces it with the next packet status, if any. It is used to get from one packet to the next in the RX FIFO. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-2 The host can also use this command to discard packets that are in error or are not needed. One reason for discarding packets is that they do not match any multicast address currently enabled through the protocol interface. 01001 TX Enable This command enables the Ethernet controller transmitter. It does not initiate transmission of a packet, which will not occur until at least the TX Start threshold bytes of the packet (or the entire packet) are in the TX FIFO. At power-up, the transmitter is disabled and must be enabled with this command. To disable, use TX Disable. Transmit errors will also disable the transmitter. 01010 TX Disable This command disables the Ethernet controller transmitter. If a packet is currently being transmitted (that is, it has been presented to the Ethernet controller), issuing this command will not stop the transmission. The transmitter will be disabled after the packet has been completely transmitted (or has reached a nonrecoverable error). The transmitter is disabled on power-up, and can also become disabled as a result of a transmit error. 01011 TX Reset (000 0000 0000) This command empties the TX FIFO. It disables the Ethernet controller transmitter. It also resets the TX Available and TX Start thresholds to defaults. If a packet is currently being transmitted, the transmit will be aborted and a bad CRC generated on the packet. After an underrun or jabber error on transmit, a TX Reset command is required the transmitter is reenabled. Do not issue TX Reset unless it is absolutely required. The argument to this command must be all zeros. 01100 Request Interrupt This command sets the Interrupt Requested bit in the Status register, causing an interrupt whenever that interrupt bit is unmasked. 01101 Acknowledge Interrupt (000 xxxx xxxx) This command acknowledges the interrupt reasons specified in the argument. These bits are laid out identically to those in the Status register. If a bit is set, it acknowledges that interrupt reason, and will in some cases turn off the bit in the Status register. In other cases, the bit in the Status register is wired to the adapter state, and that state must be changed in order to turn the bit off. In this case, setting the bit in the Acknowledge Interrupt command has no effect. If a bit is set in the command and that bit is not set in the Status register, nothing happens. For each bit, the following specifies whether or not acknowledging it will force the Status bit off. 0000 0001 Interrupt Latch This command turns off the Status register bit, releasing the interrupt. This bit must be acknowledged after all the interrupt reasons have been processed or masked off. This bit must be acknowledged before the End-of-Interrupt (EOI) command is issued to the Programmable Interrupt Controller (8259 PIC). 3Com 3C509 and 3C509-TP Technical Reference Guide 6-3 0000 0010 Adapter Failure This command does nothing. The reason bit in the FIFO Diagnostic register (Bit 13 or Bit 10) must be cleared to recover from this state. 0000 0100 TX Complete This command does nothing. The host must write the TX Status register (popping it) to turn the bit off (assuming there are no other transmit completions pending). 0000 1000 TX Available This command turns off the Status register bit and resets the TX Available threshold to its disabled value. The Set TX Available Threshold command must be reissued each time it is required. 0001 0000 RX Complete This command does nothing. To turn off the Status register bit, the host must read the remainder of the packet out of the RX FIFO (unless there is another complete packet in the RX FIFO) 0010 0000 RX Early This command turns off the Status register bit. RX Early will remain off for the duration of this packet unless the RX Early threshold is reprogrammed. To change the RX Early threshold without having this bit turn on again, reprogram the threshold before acknowledging the RX Early bit. See the Set RX Early Threshold command for more details. 0100 0000 Interrupt Requested This command turns off the Status register bit. 1000 0000 Update Statistics This command does nothing. To turn off the Status register bit, read the statistics. This will reset them all to zero. 01110 Set Interrupt Mask (000 xxxx xxxz) This command sets the Interrupt mask; each bit that is set enables interrupts from that interrupt source. To mask off all interrupts from the adapter, set the Interrupt mask to zero. When an interrupt reason is masked off, the corresponding interrupt bit in the Status register is still readable, although it is no longer a source for interrupts. Use the Set Read Zero mask command to force the bits to read as zero. The bits are laid out identically to their locations in the Status register. At power-up, the Interrupt mask defaults to zero. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-4 01111 Set Read Zero Mask (000 xxxx xxxz) This command sets the Read Zero mask; each bit that is clear causes the corresponding bit in the Status register to read as zero. The Read Zero mask is applied to the Status register before the Interrupt mask. Clearing a bit in the Read Zero mask also prevents it from causing interrupts. To force all interrupt sources to zero, set the Read Zero mask to zero. Use the Set Interrupt mask command to disable interrupts and still allow the bit in the Status register to be readable. The bits are laid out identically to their locations in the Status register. At power-up, the Read Zero mask defaults to zero. NOTE: The Interrupt Latch bit cannot be forced to zero with this command. 10000 Set RX Filter (000 0000 xxxx) This command sets the Receive filter as follows: 0001 Individual address 0010 Group (multicast) addresses 0100 Broadcast address 1000 All addresses (promiscuous mode) At power-up, the Receive filter defaults to zero, and must be set with this command before any packets can be received. Enabling group address reception implies broadcast reception. 10001 Set RX Early Threshold (xxx xxxx xxzz) This command sets the RX Early threshold. Once the RX Early threshold bytes of a packet have been received, an RX Early interrupt will be generated to the host. A multiple of four with a range of 0 to 2032 bytes is used. To disable, set to 2032 (the power-on default). Truncated to a dword multiple. Normal collisions may be received as bad packets by the host if the RX Early threshold is set to less than 60 bytes (one slot time). The driver must be prepared to increase this value if too many bad packets result because the setting is less than 60 bytes. It must be possible to reprogram this value in the middle of receiving a packet and still have it go off when appropriate. This feature might be used by the software to try and take an interrupt just before its computed packet length, to overlap some of the packet reception with the expected interrupt latency. To do this, and to generate another interrupt, the RX Early threshold must be reprogrammed after the RX Early interrupt has been acknowledged. NOTES: 1. The RX Complete bit masks the RX Early bit. Whenever RX Complete is set, RX Early will be clear. Also, when the Ethernet controller signals the end of a receive packet, thereby clearing the RX Incomplete bit on the bottom of the RX Status stack, RX Early will be automatically acknowledged/cleared. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-5 2. The current design hides 16 bytes of an incomplete packet from the host. Thus if RX Early is set to 24, 40 bytes must be received before the packet becomes visible to the host. At that point RX Status shows 24 bytes received. When the packet reception is complete, the 16 bytes will be added to the byte count in the RX Status register all at once. Therefore, the software does not need to be aware of this process. Future revisions of the ASIC will not hide bytes; it is not advisable to set RX Early to values less than eight. It is suggested that software derive a variable and set it to 16 based on the ASIC revision level of 1 (refer to "Diagnostic Registers" later in this chapter). 10010 Set TX Available Threshold (xxx xxxx xxzz) This command sets the TX Available threshold, which specifies the number of free bytes required by the host. A TX Available interrupt will be generated when the number of free bytes in the TX FIFO exceeds this threshold. This allows the host to return and wait for sufficient free space before continuing to copy data to the TX FIFO. A multiple of four with a range of 0 to 2044 bytes is used. Setting this threshold to 2044 (the power-on default) disables it. Once the TX Available bit is acknowledged, the threshold returns to 2044, and it will not go off again. Therefore, the Set TX Available threshold command must be reissued each time the driver decides to return control until sufficient space is available to continue. 10011 Set TX Start Threshold (xxx xxxx xxzz) This command specifies the number of bytes required before the adapter may start transmitting the packet. The packet will start transmitting either when the number of bytes in the TX FIFO exceeds the TX Start threshold or when the entire packet has been copied to the TX FIFO. A multiple of four with a range of 0 to 2040 bytes is used. Setting this threshold to 2040 (the power-on default) disables it, so that packet transmission starts only when the entire packet has been moved to the TX FIFO. This threshold can be used in combination with TX Available to avoid transmit underruns. Reset the TX Start threshold to more than the number of bytes of a packet that were copied to the TX FIFO before it ran out of space. This guarantees that no underrun will occur before the TX Available interrupt comes in. However, the transmit packets may not go out with the minimum interpacket gap. 10101 Statistics Enable This command enables the collection of statistics by the adapter. These statistics are maintained in Window 6 registers. At power-up, statistics collection is disabled and must be enabled with this command. Before any of the statistics in Window 6 are read, statistics collection must be temporarily disabled with the Statistics Disable command. Once the statistics have been read, statistics can be reenabled with this command. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-6 10110 Statistics Disable This command disables the collection of statistics by the adapter. At power-up, statistics collection is disabled. The adapter latches statistics update requests while the statistics are disabled. As long as statistics are only kept disabled long enough to read in the statistics, no statistics will be lost in the process. Refer to "Statistics Registers" later in this chapter for more information. 10111 Stop Coaxial Transceiver This command shuts off the DC-DC converter that drives the on-board coaxial transceiver. This command might be used for diagnostic or power-management reasons. The host must delay at least 800 us after issuing this command before using the AUI interface. This can be accomplished by starting the timer and waiting until it pegs at its maximum value of FFh. 6.2 Status Register Function: Reports the adapter state, including window number and the reasons for the interrupt. Location: All windows/Port 0E Type: Read only Size: 16 bits (8-bit reads also allowed to either byte) Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Window |CIP| Reserved | US| IR|RXE|RXC|TXA|TXC| AF| IL| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 15-13 Window Number (0-7) Bit 12 Command-in-Progress Bit 11 Reserved Bit 10 Reserved Bit 9 Reserved Bit 8 Reserved Bit 7 Update Statistics* Bit 6 Interrupt Requested* Bit 5 RX Early* Bit 4 RX Complete* Bit 3 TX Available* Bit 2 TX Complete* Bit 1 Adapter Failure* Bit 0 Interrupt Latch Those bits marked with an asterick (*) cause an interrupt when set, assuming they are not masked off in either the Interrupt mask or the Read Zero mask. These bits can be forced to zero with the Read Zero mask, disabled as a source of interrupts with the Interrupt mask, or acknowledged with the Acknowledge Interrupt command. All of these have identical layouts for these bits. NOTE: The low byte contains all of these interrupt causes and can be used directly as an index into a dispatch table if desired. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-7 Bit 0 Interrupt Latch This bit is latched when the adapter raises an interrupt to the host. The bit is cleared when it is acknowledged. In a shared interrupt environment (not ISA), this bit can be used to determine the source of the interrupt. NOTE: This bit does not cause an interrupt, it is the interrupt. Bit 1 Adapter Failure* An error occurred that the adapter was unable to recover from. Possible causes are: - Transmit overrun (host writes more data than there is room for) - Receive underrun (host reads data that is not yet available) - Internally detected hardware errors as yet undefined Various diagnostic registers are available to determine the cause of the failure. The host must issue the appropriate Reset command to clear this condition and recover. Bit 2 TX Complete* The adapter has finished transmitting a packet and has updated the TX Status register with its transmit status (with the TX Complete bit set). To clear this bit, the host writes the TX Status register to pop the transmit status off the TX Status stack. NOTE: A TX Complete interrupt is signaled only for packets that failed to transmit successfully or packets with a transmit preamble bit set specifically for an interrupt on successful transmission. If TX Status indicates a transmit underrun or jabber error, then a TX Reset command will be necessary. In any event, a TX Enable command will be required to restart the transmitter after any error. Refer to "TX Status" later in this chapter for more information. Bit 3 TX Available* The number of free bytes in the TX FIFO now exceeds the TX Available threshold. Bit 4 RX Complete* A complete packet is available in the RX FIFO. This bit is set if the Incomplete bit in the RX Status register is zero. To clear this bit, the host must read the packet out of the RX FIFO. A receive overrun requires no special action on the part of the host, other than discarding the packet. Bit 5 RX Early* Sufficient bytes of the current packet have been received to exceed the RX Early threshold, although the packet is not yet complete. See the Set RX Early Threshold command for more details. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-8 Bit 6 Interrupt Requested* This bit is set by the Request Interrupt command. To clear this bit, simply acknowledge it. It provides a way for the driver to request an interrupt for its own purposes. Bit 7 Update Statistics* This bit indicates that one or more of the statistics counters is nearing an overrun condition (typically half its maximum value). The host must read out all of the statistics and update its local counters from them (zeroing the counters on the adapter in the process and thereby clearing this bit). Bit 12 Command-in-Progress This bit is set to indicate that the last command issued is still being processed by the adapter. It need be checked only after one of the commands has been issued that may require more than a single I/O cycle for completion (that is, those marked with an asterick [*] in the command). No other commands may be issued until this bit has been reset. This check must be done with interrupts disabled. Bits 15-13 Window Number This bit reflects the current window set and must be visible in every window. 6.3 FIFO Registers 6.3.1 RX Status Function: Contains the status and number of bytes for the receive packet at the top ofthe RX FIFO. Location: Window 1/Port 08 Type: Read only Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | I | E | Error Type| RxBytes | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 15 Incomplete (1 = RX packet is incomplete or RX FIFO empty) Bit 14 Error (1 = Error in RX packet, 0 if incomplete or no error) Bits 13-11 Type of error (Undefined if no error, highest priority first) 1000 = Overrun 1011 = Runt Packet Error 1100 = Alignment (Framing) Error 1101 = CRC Error 1001 = Oversize Packet Error (>1514 bytes) 0010 = Dribble Bit(s) 0000 and all other codes = No Errors Bits 10-1 RX Bytes (0-1514) 3Com 3C509 and 3C509-TP Technical Reference Guide 6-9 This register is a ripple-through FIFO that advances one position (popping the stack) after issuing an RX Discard command. As a packet is received off the wire, its corresponding RX Status entry (visible if this is the only packet in the RX FIFO) has its RX Bytes incremented. Until the end of the packet is received and placed in the RX FIFO, the Incomplete bit will remain set and the Error bit will be clear. Once the packet has been completely moved into the RX FIFO, the Incomplete bit will be cleared and the Error bit and the error type will be set appropriately. The error bits encode the packet status. If multiple errors occurred, the highest priority error will be shown. For example, a runt with a CRC error will be flagged as a runt. If a packet is flagged as overrun, the host must not rely on the contents of the packet (it may have holes in it where the data was lost). A packet with only a Dribble Bit error is a valid packet and must be read by the driver software. The Dribble Bit indication is for informational purposes only. An oversized packet (longer than 1514 bytes) will continue to be received correctly until it reaches 1792 bytes, when it will be cut off and the remainder discarded. If the packet is not read from the RX FIFO until the Incomplete bit is cleared, then the RX Bytes field will show the packet length, assuming there were no errors. As the packet is read from the RX FIFO, RX Bytes will be decremented. This can be done before the packet is completely received; the RX Bytes will never show the actual packet size. RX Bytes reflects the number of bytes of packet data that were received, and does not include any padding to a dword multiple. The current implementation hides 16 received bytes from the host, so that the RX Bytes count will always be 16 less than the number of bytes received off the wire until the packet is completed. At that point, RX Bytes will be incremented by 16 bytes. A packet becomes visible to the host through RX Status once the number of bytes received (minus the hidden 16 bytes) exceeds the minimum of 60 and the RX Early threshold. At that point, the number of bytes received (minus 16) becomes visible in RX Bytes and will continue to increment as more bytes are received. If an error in the packet is signaled before the packet becomes visible to the host, the packet is discarded. Otherwise, the packet will show up in the RX Status stack flagged with an error. When reading the last byte of the actual packet data, RX Bytes will show 1. If the packet was not a multiple of four in length, there may be more bytes to read because of padding. After reading the last byte, RX Bytes will change to 0. After reading one more byte, it will change to -1 (11111111111), then -2 (11111111110) after one more byte, then -3, and so on. RX Bytes can go as far as -5. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-10 6.3.2 TX Status Function: Reports the transmit status of a completed transmission. Reading this register pops the transmit completion stack. Location: Window 1/Port 0B Type: Read only Size: 8 bits Bit Description: 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+ | C | I | J | U | MC|TSO| Undef | +---+---+---+---+---+---+---+---+ Bit 7 Complete (1 = TX is Complete) Bit 6 Interrupt on Successful Transmission Requested Bit 5 Jabber Error (TP only, TX Reset required) Bit 4 Underrun (TX Reset required) Bit 3 Maximum Collisions Bit 2 TX Status Overflow Bits 1-0 Undefined The hardware uses the TX Status register to stack information about transmit completions that must be signaled to the driver. Whenever a transmit is completed that must be signaled to the host (either it failed, or the preamble specified an interrupt on successful transmission), the adapter pushes the status onto the TX Status stack. When the host fields the TX Complete interrupt, it can read TX Status to determine the transmit status. The TX Complete bit will not be set if the stack is currently empty (nothing to pop). Whenever the driver writes the TX Status register and the TX Complete bit is set, this pops the stack, and the next transmit complete status can be read (if any). Popping everything off the TX Status stack turns off the TX Complete interrupt in the Status register. Do not write to the TX Status register unless you have read a non-zero value at this location. To do so may clear a yet-to-be seen transmit status. If an error is indicated, then the transmitter has been disabled and must be reenabled with the TX Enable command. If the error was a maximum collisions error, then nothing more is required. If the error was a jabber or an underrun, however, then a TX Reset command is required before the TX Enable can be issued. When the completion of a packet is signaled to the host, the packet has been discarded from the TX FIFO. If it is to be retransmitted, it must again be copied to the TX FIFO. If the error occurred while the packet was still being copied to the adapter, the host can continue to copy the packet to the adapter, since the transmitter is disabled. NOTE: Free Transmit Bytes may take an additional I/O cycle to update after the packet transmission has been completed. The Interrupt on Successful Transmission Requested bit reflects the same bit in the TX preamble for this packet. The protocol can use this bit to determine whether this is the packet on the head of some "to be completed" queue, or simply a packet that it has forgotten. In either case the host can use this opportunity to update any statistics counters it may have. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-11 The TX Status Overflow bit, if set, indicates that the TX Status stack is full, and as a result the transmitter has been disabled. Simply reading the TX Status register clears this condition, so the only other action required is a TX Enable command. The TX Status stack can hold exactly 31 entries, so this condition is unlikely in normal operation. No packets are dropped or confirmations lost when this condition is entered. 6.3.3 RX PIO Data Read Function: Used to read data from the RX FIFO. Location: Window 1/Port 00 and Port 02 Type: Read only Size: 16 bits/8 bits allowed from lower byte Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | RX PIO Data Read | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 15-0 RX PIO Data Read This register is used to read data from the RX FIFO. A word read will pop a word off the head of the RX FIFO. A byte read to the low-order byte of the register will pop a byte off the RX FIFO. Byte reads to the high-order byte are not allowed. Double word reads are also possible when this register is used in combination with the one after it (which is treated identically by the hardware). Such reads pop two successive words off the RX FIFO, returning the first in the low-order word, and the second in the high-order word. Although byte and word reads are allowed, the packet data is always padded to a dword boundary. The RX Discard command can be used to skip this padding. 6.3.4 TX PIO Data Write Function: Used to write data to the TX FIFO. Location: Window 1/Port 00 and Port 02 Type: Write only Size: 16 bits/8 bits allowed to lower byte Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | TX PIO Data Write | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 15-0 TX PIO Data Write This register is used to write data to the TX FIFO. A word write will push a word onto the tail of the TX FIFO. A byte write to the low-order byte of the register will push a byte onto the TX FIFO. Byte writes to the high-order byte are not allowed. Double word writes are also possible when this register is used in combination with the one after it (which is treated identically by the hardware). Such writes push two successive words on the TX FIFO; the low-order word first, then the high-order word. Although byte and word writes are allowed, the packet data must always be padded to a dword boundary. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-12 6.3.5 Free Receive Bytes Function: Returns the number of bytes available in the RX FIFO. Location: Window 3/Port 0A Type: Read only Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | Free Receive Bytes | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 10-2 Free Receive Bytes (0-2044) Free Receive Bytes equal to 0 imply that the RX FIFO is full. 6.3.6 Free Transmit Bytes Function: Returns the number of bytes available in the TX FIFO. Location: Window 1/Port 0C and Window 3/Port 0C Type: Read only Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | 0 | 0 | 0 | Free Transmit Bytes | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 10-2 Free Transmit Bytes (0-2044) Free Transmit Bytes equal to 0 imply that the TX FIFO is full. When Free Transmit Bytes are not zero, that number of bytes can be written to the TX FIFO without an overrun. 6.4 Timer Register Function: Interrupt latency measurement Location: Window 1/Port 0A Type: Read only Size: 8 bits Bit Description: 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+ | Timer | +---+---+---+---+---+---+---+---+ Bits 7-0 Timer The Timer register is a free-running 8-bit counter that is running off a 10 MHz/32 clock (period = 3.2 us, the quadbyte rate). The count is reset to zero whenever the interrupt output transitions from inactive to active. This allows the driver to make interrupt latency measurements and evaluate other system-dependent parameters. When the Timer bit reaches 255, it stops incrementing. To use this counter for more general measurements at driver initialization time, disable interrupts and issue a Request Interrupt command to reset the counter. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-13 6.5 Statistics Registers The statistics registers in Window 6 make available various counters maintained by the adapter. Before reading any of these registers, the host must disable statistics collection by issuing the Statistics Disable command. Reading any statistic resets it to zero. Counters that are 16 bits in the interface must be read as words. Counters that are 8 bits must be read as bytes. After the counters have been read, the Statistics Enable command must be used to reenable statistics collection. The size of the internal counters on the adapter varies. Several counters are 6 bits, and several are only 4 bits. Counters less than 8 bits long get zero fill to 8 bits across the interface. An Update Statistics interrupt is generated when any statistic reaches half its maximum value (that is, its upper bit gets set). The exceptions are the two 16-bit counters that generate an Update Statistics interrupt only when the upper 3 bits are set (so they can use more of their range before they require reading). The proper method for servicing this interrupt is to read all statistics and to accumulate proper 32-bit values in host memory. This will reset each statistic in turn and update all statistics in a relatively coherent manner. There is no bit available to indicate which counter reached half its value. Once all of the counters have been read, the Update Statistics bit in the Status register will be cleared. The adapter latches statistics update requests while the statistics are disabled. As long as statistics are kept disabled only long enough to read the statistics in, no statistics will be lost in the process. Writing to the statistics registers is supported to allow for simple debugging. When a value is written to the statistics registers, it is added to the statistics current value. This is done using much of the normal statistics collection state machine. Statistics collection must be enabled for the addition to take place. The following network statistics are defined primarily according to the NDIS specification, version 2.01. 6.5.1 Statistics Function: Read and zero internal counters Location: Window 6/Ports 00 thru 0C Type: Read/write (reading resets counter) Size: 8 bits/16 bits (16 bits as words, all else as bytes) Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Counter Value | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ or 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+ | Counter Value | +---+---+---+---+---+---+---+---+ Bits 15-0 or 7-0 Counter Value 3Com 3C509 and 3C509-TP Technical Reference Guide 6-14 These counters collect statistics of transmit or receive events as long as statistics are currently enabled. Statistics must be disabled before they can be read. Reading a statistic also zeroes it. To check proper function of the statistics logic, values can also be written to the statistics. Writing a value will add that value to the current statistic as long as statistics are currently enabled. The 16-bit statistics must be read/written as a word; all others must be read/written as bytes. FIFO loopback can cause the various statistics registers to return indeterminate values. After leaving FIFO loopback, enable statistics, then disable and read all the statistics to clear them. Port Offset Size (bits) Description of Statistic ----------- ----------- ------------------------ 0C 16 Total bytes transmitted successfully with no errors noted. 0A 16 Total bytes received successfully. This number excludes runts, overruns, and frames discarded before completion. 08 8 Total transmit deferrals. 07 8 Total frames received successfully. This number excludes runts, overruns, and frames discarded before completion. 06 8 Total frames transmitted successfully with no errors noted. 05 8 Total receive frames discarded because of RX FIFO overrun. This includes only those packets seen by the host as RX overruns. It does not include those discarded without a trace because the RX FIFO was completely full. 04 8 Late collisions on transmit. 03 6 Total frames transmitted after one collision. 02 6 Total frames transmitted after multiple collisions. 01 4 Total frames transmitted with no CD heartbeat (SQE). This statistic is only collected if the SQE Statistic Enable bit (bit 3 of the Media Type and Status register) is set. Since certain external transceivers do not support SQE, this statistic can be disabled to avoid excessive update statistics. 00 4 Total carrier sense lost during transmission. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-15 6.6 Diagnostic Registers 6.6.1 Media Type and Status Function: Reports media type/configuration and status. Location: Window 4/Port 0A Type: Read/write (only certain bits are writable) Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |AUI|BNC|IEN|SQE|LKC|POL|JAB|USQ|LKE|JBE|CRS|COL|SEN| 0 | 0 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 15 1 = AUI disable (read only). Bit 14 1 = BNC transceiver (read only). Bit 13 1 = Internal encoder/decoder (read only). Bit 12 1 = SQE present (read only). Bit 11 1 = Link beat correct (TP) (read only). Bit 10 1 = Polarity swap (TP) (read only). Bit 9 1 = Jabber (TP) (read only). Bit 8 1 = Unsquelch (TP) (read only). Bit 7 1 = Link beat enabled (writable). Defaults to 0 (disabled). Must be set by software only if the internal TP transceiver is in use. Link Beat must be disabled in ENDEC loopback mode. Bit 6 1 = Jabber enabled (writable). Defaults to 0 (disabled). Must be set by software only if the internal TP transceiver is in use. This also enables the polarity reversal state machine. Bit 5 1 = Carrier sense (CRS) (read only). Bit 4 1 = Collision (read only). Bit 3 1 = SQE Statistics Enable. Defaults to 0 (disabled). Must be enabled by software at startup, and disabled only if the number of SQE errors becomes excessive in AUI mode, which probably indicates that the external transceiver does not support SQE. Bits 2-0 Unassigned, read as zero. 6.6.2 Net Diagnostic Port Function: Supports the network diagnostic. Location: Window 4/Port 06 Type: Read/write (only certain bits are writable) Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |EXL|ENL|ECL|FFL|TXE|RXE|TXT|TXR|STE| U | ASIC Revision |TLV| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 15 1 = External loopback (read/write). Setting this bit enables an external loopback mode allowing simultaneous transmit and receive (TP, BNC, or AUI external loopback mode). Bit 14 1 = ENDEC loopback (read/write). Setting this bit enables a loopback mode at the output of the encoder/decoder. You must disable link beat through the Media Type and Status register before enabling ENDEC loopback. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-16 Bit 13 1 = Ethernet Controller loopback (read/write). Setting this bit enables loopback at the output of the Ethernet Controller transceiver. Bit 12 1 = FIFO loopback (read/write). This loopback returns data through the FIFO at the interface between the Ethernet Controller transmitter and the FIFO. In FIFO loopback mode, overruns and underruns are not possible - the data is simply moved between the FIFOs as it is available. Bit 11 1 = TX enabled (read only). Can be cleared by TX Reset, TX Disable, or as a result of a transmit error. Bit 10 1 = RX enabled (read only). Bit 9 1 = TX transmitting (read only). Set if you are transmitting or deferring before transmitting. Bit 8 1 = TX Reset required (read only). Set if a jabber or underrun error occurs, both of which require a TX Reset for recovery. Bit 7 1 = Statistics enabled (read only). Bit 6 Unassigned. Bits 5-1 ASIC revision level. Currently 1. Future revisions of the ASIC that change the functionality in any significant way will modify this value. Bit 0 1 = Test low voltage detector. Setting this bit to 1 will reset the ASIC if the low- voltage detector is functional. This bit defaults to zero at power-up/reset. This bit must remain zero except for ASIC functional testing. 6.6.3 FIFO Diagnostic Port Function: Supports the FIFO diagnostics. Location: Window 4/Port 04 Type: Read/write (only certain bits are writable) Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |RXR|RES|RXU|RSO|RXO|TXO| RES | Built-in Self Test | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 15 1 = RX receiving (read only). Set when a packet is being received into the RX FIFO. Bit 14 Reserved. Bit 13 1 = RX Underrun (read only). Generates Adapter Failure interrupt. Requires RX Reset or Global Reset command to recover. An RX Underrun is generated only when you read past the end of a packet - reading past what has been received so far will give bad data. Bit 12 1 = RX Status Overrun (read only). Set when there are already eight packets in the RX FIFO. While this bit is set, no additional packets are received. Requires no action on the part of the host. The condition is cleared once a packet has been read out of the RX FIFO. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-17 Bit 11 1 = RX Overrun (read only). Set when the RX FIFO is full (there may not be an overrun packet yet). While this bit is set, no additional packets will be received (some additional bytes can still be pending between the wire and the RX FIFO). Requires no action on the part of the host. The condition is cleared once a few bytes have been read out of the RX FIFO. Bit 10 1 = TX Overrun (read only). Generates Adapter Failure interrupt. Requires the TX Reset or Global Reset command to recover. Disables transmitter. Bits 9-8 Unassigned. Bits 7-0 These bits are used to execute the Built-in Self-test (BIST) circuitry for both the RX and TX FIFOs. These bits will give 100% fault coverage for stuck-on faults, transition faults, coupling faults, and addressing (decoder) faults. They are intended primarily for testing the ASICs, but can also be included in a diagnostic self-test. The two tests, RX and TX, are run independently. To perform either test, first reset, then set the appropriate BIST bit. Loop until the BC is set (this takes approximately 500 ms). If BF is set, the test failed. Otherwise check for BF stuck at 0. To do this, set BFC, then reset it. BF must now be set. If not, BF is stuck. If everything passes, then the RAM is fully functional. All read-only bits default to reset (0) at power-up. Bit 7 RX BIST (write only). Bit 6 RX BFC (write only). Bit 5 RX BF (read only). Bit 4 RX BC (read only). Bit 3 TX BIST (write only). Bit 2 TX BFC (write only). Bit 1 TX BF (read only). Bit 0 TX BC (read only). 6.6.4 Host Diagnostic Port Function: Supports host interface diagnostic. Location: Window 4/Port 02 Type: Read/Write (only certain bits are writable) Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Reserved | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 15-0 Reserved. 3Com 3C509 and 3C509-TP Technical Reference Guide 6-18 6.6.5 TX Diagnostic Port Function: Supports Ethernet Controller transmit diagnostic. Location: Window 4/Port 00 Type: Read/Write (only certain bits are writable) The The writable bits all default to zero at power-up/reset. They must remain zero except when writing test vectors. Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Attempt Count | testo[3..0] | testi[7..0] | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bits 15-12 Attempt counter. Incremented on each collision. Bit 11 Ethernet Controller testo[3] (read only). Bit 10 Ethernet Controller testo[2] (read only). Bit 9 Ethernet Controller testo[1] (read only). Bit 8 Ethernet Controller testo[0] (read only). Bit 7 Ethernet Controller testi[7]. Bit 6 Ethernet Controller testi[6]. Bit 5 Ethernet Controller testi[5]. Bit 4 Ethernet Controller testi[4]. Bit 3 Ethernet Controller testi[3]. Setting this bit forces the random counter to 1, thereby speeding up the retry time after a collision. Bit 2 Ethernet Controller testi[2]. Bit 1 Ethernet Controller testi[1]. It also increases the speed of an internal clock that times the EEPROM accesses. Bit 0 Ethernet Controller testi[0]. It also increases the speed of the timer and jabber counter. 6.6.6 Ethernet Controller Status Function: Provides access to Ethernet Controller status. Location: Window 4/Port 08 Size: 16 bits Bit Description: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |TXD|TXR|TXU|TMC|TLC|TSE|TCA|TES|RRO|RXD|RFE|RXO|RFC|RDR|RXS|RXT| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Bit 15 Ethernet Controller TX DONE(read only). Bit 14 Ethernet Controller TX RETRY (read only). Bit 13 Ethernet Controller TX UNDERRUN (read only). Bit 12 Ethernet Controller TX MAX COLL (read only). Bit 11 Ethernet Controller TX LATE COLL (read only). Bit 10 Ethernet Controller TX SQE ERR (read only). Bit 9 Ethernet Controller TX LCAR (read only). Bit 8 Ethernet Controller TX END SLT TIME (read only). Bit 7 Ethernet Controller RX REJECT OUT (read only). Bit 6 Ethernet Controller RX DONE (read only). Bit 5 Ethernet Controller RX FRAME ERR (read only). Bit 4 Ethernet Controller RX OVERRUN (read only). Bit 3 Ethernet Controller RX FCS ERR (read only). Bit 2 Ethernet Controller RX DRIBBLE (read only). Bit 1 Ethernet Controller RX SHORT (read only). Bit 0 Ethernet Controller RX TESTEN (read/write). 3Com 3C509 and 3C509-TP Technical Reference Guide 6-19 Chapter 7 Adapter Configuration and Enable The 3C509 adapter supports a variety of configuration options controlled by a set of configuration registers. It also supports two adapter activation mechanisms, one for ISA machines and the other for EISA machines. NOTE: Once activated, the adapter can be deactivated only by a Global Reset command. 7.1 Automatic Configuration at Power-on Reset After reset (power-on reset, Configuration Control register bit 2, Global Reset command, or ID Global Reset command) the adapter copies the eighth, ninth, and third words of the EEPROM into the Address Configuration register, the Resource Configuration register, and the Product ID register. The I/O base address configuration is also written at this time. NOTE: The driver software is responsible for reading the station address out of the EEPROM and writing it into the Ethernet controller. 7.2 ISA Activation Mechanism If the I/O base address configuration is set to an ISA base address, then the ISA activation mechanism is selected. In this mode, memory read accesses to the boot PROM are always enabled after automatic configuration is completed, but I/O accesses to the adapter's I/O base address are disabled until the ID Sequence State machine (IDS) activates them. See Figure 7-1. +--------+ +-------+ ID Complete +------+ +------+ Reset | | | |---------------> | Activate | | ------->AUTOINIT|-->ID_WAIT| |ID_CMD|---------->ACTIVE| | | | <---------------| | | | +--------+ +-------+ ContendFail +------+ +------+ +TestFail +GotoWAIT Figure 7-1. ID Sequence State Machine (IDS) WARNING: The adapter is not visible to the software until after the automatic configuration logic has finished reading the adapter configuration EEPROM. This takes 310 us after a global reset. A global reset can be caused by power-on reset (RESETDRV), a Global Reset command written to the Command register (port 0E), an ID Global Reset command written to the ID command port, or setting the RST (reset) bit (bit 2) in the Configuration Control register (port 04). After the automatic configuration completes, the IDS is in its initial state (ID_WAIT) (see Figure 7-1), and it monitors all write access to I/O port 01x0h, where x is any hex digit. If a zero is written to any one of these ports, then that address is remembered and becomes the ID port. A second zero written to that port resets the ID sequence to its initial state. The IDS watches for the ID sequence to be written to the ID port. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-1 The ID sequence is a sequence of 255 bytes defined by the following algorithm: mov cx, 0FFh mov dx, IDport mov al, 0FFh @@1: out dx, al shl al jnc @@2 xor al, 0CFh @@2: loop @@1 The sequence starts with the value 0FFh and ends with 98h (if the adapter is in test mode, the sequence ends with 69h, the eighth byte). If at any point in the sequence an incorrect value is written, the sequence is reset to its initial value of 0FFh. Since the value zero never appears in the ID sequence, writing a zero always resets the sequencer and the ID Port. When the complete sequence has been written, the IDS enters the command state. In the ID_CMD state the IDS responds to both I/O reads and writes to the ID port. I/O writes to the ID port are interpreted as commands. The following commands are supported: 00 to 7F Go to ID_WAIT state. Wait for next ID sequence. 80 to BF Read EEPROM word n. Address n is the last six bits of the command. EEPROM data is read into the EEPROM data register . C0 to CF Global Reset. Resets adapter to the same state as power- on reset (POR). D0 to D7 Set adapter tag register to n where n is last three bits of the command. If adapter tag register is non-zero, then the adapter will not respond to reads of the ID port. If the adapter tag register is non-zero, then the adapter will ignore the commands in the D1 to D7 range. D8 to DF Test adapter n where n is the last 3 bits of the command. If the adapter tag register is not equal to n, then go to the ID_WAIT state else NOP. E0 to FE Activate adapter, write the last five bits of the command into the low five bits of the Address Configuration register that controls the I/O base address, and return to the ID_WAIT state. FF Activate the adapter at the preconfigured I/O base address and return to the ID_WAIT state. In the ID_CMD state, I/O reads to the ID port are treated as a contention test. During a contention test, the adapter drives bit 15 of the EEPROM Data register out onto bit 0 of the host data bus, using an open drain driver. If there are multiple adapters in the system and one of them drives out a "1" and the other drives out a "0," then both adapters and the host system will see (read) a "0" on bit 0 of the host data bus. At the end of the read cycle the adapter samples the data on bit 0 of the host data bus. If the data does not match what was driven out, then the IDS has a contention failure and returns to the ID_WAIT state. The EEPROM Data register is shifted (rotated) left one bit. Meanwhile, the host gets one bit of configuration data in bit 0 of the AX Register with each read cycle. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-2 This mechanism (ID_WAIT state and ID_CMD state) continues to function even after the adapter is activated. This means the adapter will respond to the software in the same way after either a cold boot or a warm boot. Use the following algorithm to activate a particular adapter, assuming multiple randomly configured adapters exist in the host system. 1. Power-up system. All adapters auto-initialize and then enter the ID_WAIT state. In this state the adapter only responds to writes to the ID port. The ID port is the last I/O port in the range of 100h to 1FFh that has had a zero written to it. 2. Write two 0 bytes and then the ID sequence to the ID port. All adapters enter the ID_CMD state. 3. Select EEPROM data to contend on by writing an EEPROM read command to the ID port. 4. Read the ID port 16 times. Any adapter that gets a contention failure will return to the ID_WAIT state. 5. Repeat steps 3 and 4 until contention criteria (station address, I/O base address, ROM base address) have been met and only a single adapter is left in the ID_CMD state. 6. Either tag the adapter with the Set Tag command or activate the adapter with the Activate command. 7. Repeat steps 1 through 6 until the desired adapter is found and activated. 8. Enable DRQ and IRQ drivers by setting the ENA (enable) bit (bit 0 of the Configuration Control register). 7.3 EISA Activation Mechanism If the I/O base address configuration is set to the EISA slot-specific addressing mode, then the EISA activation mechanism is selected. After automatic configuration, the adapter will respond to I/O accesses in the range of xC80 to xC8F where the window 0 register set is always mapped. The EISA motherboard BIOS will check the Manufacturer Code and Product ID registers, overwrite the Address Configuration and Resource Configuration registers, and then set the Enable bit in the Configuration Control register to enable the adapter. Once enabled, the adapter will respond to I/O accesses in the range of x000 to x00F where the complete adapter register set is mapped, to read access to its boot PROM address range (if any) and to enable the IRQ and DRQ drivers. If the adapter is not installed in an EISA machine, then the IDS state machine is still enabled (see the preceding section) and can be used instead. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-3 7.4 Window 0 Register Set The window 0 register set controls the configuration of the adapter and provides access to the adapter's EEPROM. The window 0 register set correctly responds to both byte and word I/O cycles. Also, the IRQ and DRQ drivers are disabled while window 0 is selected. 7.4.1 Manufacturer Code Register (Read Only - Offset 0) This is the encoded form of 3Com's registered EISA manufacturer code "TCM". The manufacturer code is stored in a byte-swapped format. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 6 | D | 5 | 0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ 7.4.2 Product ID Register (Read Only - Offset 2) The automatic configuration logic loads this register. The product number is stored in a byte-swapped format. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |Product ID (lo)| Revision Code | Product ID (hi) | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Product Number: The Product Number is the binary coded decimal 3Com part number for this board. When this changes, a new EISA configuration file must be released. The product ID is formed by the concatenation of Bits 7-0 and Bits 15-12, where Bits 7-4 form the highest nibble and Bits 15-12 form the lowest nibble. Revision Code: The Revision Code is a 4-bit adapter revision code. Changes to this field do not require a new version of the EISA configuration file. 7.4.3 Configuration Control Register (Read/Write - Offset 4) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | 0 | 0 | PORreg | 0 | 0 | 0 | 0 | 0 |RST| 0 |ENA| +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ PORreg: POR Jumper Register. Lower six bits of the RData bus latched at the deassertion of ResetPinIn. PORreg is read only. Bit 13 0 = No AUI connector is available. 1 = AUI connector is available. Bit 12 0 = No on-board 10BASE2 transceiver is available. 1 = On-board 10BASE2 transceiver is available. Bits 11-10 0 = Reserved. 1 = Receive test mode (see IDS). 2 = Transmit test mode (see IDS). 3 = Normal operation mode. Bit 9 0 = No on-board 10BASE-T transceiver is available. 1 = On-board 10BASE-T transceiver is available. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-4 Bit 8 0 = Use external encoder/decoder. 1 = Use internal encoder/decoder. Bit 2 RST (Reset adapter) 0 = Normal operation. 1 = Reset adapter to same state as POR. Bit 0 ENA (Enable adapter) 0 = Adapter disabled. Disables DRQ and IRQ drivers. In EISA mode also disables boot PROM address decoding. 1 = Adapter enabled. 7.4.4 Address Configuration Register (Read/Write - Offset 6) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | XCVR |ROM SIZ| ROM BASE | Reserved | I/O Base | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The automatic configuration logic loads this register. XCVR (Transceiver type select): 00 = Twisted-pair (10BASE-T) transceiver enabled. 01 = AUI port enabled. Using external transceiver. 10 = Reserved - undefined. 11 = BNC (10BASE2) transceiver enabled. The software driver must issue a Start Internal Transceiver command to the Command register to start the DC- DC converter. ROM SIZE: Boot PROM window size. ROM BASE: Boot PROM base address select. ROM Size ROM Base Effective Address Window -------- -------- ------------------------ 00 0000 Disable boot PROM 00 0001 C2000h to C3FFFh 00 0010 C4000h to C5FFFh 00 0011 C6000h to C7FFFh 00 0100 C8000h to C9FFFh 00 0101 CA000h to CBFFFh 00 0110 CC000h to CDFFFh 00 0111 CE000h to CFFFFh 00 1000 D0000h to D1FFFh 00 1001 D2000h to D3FFFh 00 1010 D4000h to D5FFFh 00 1011 D6000h to D7FFFh 00 1100 D8000h to D9FFFh 00 1101 DA000h to DBFFFh 00 1110 DC000h to DDFFFh 00 1111 DE000h to DFFFFh 01 0000 Disable boot PROM 01 0001 C0000h to C3FFFh 01 001x C4000h to C7FFFh 01 010x C8000h to CBFFFh 01 011x CC000h to CFFFFh 01 100x D0000h to D3FFFh 01 101x D4000h to D7FFFh 01 110x D8000h to DBFFFh 01 111x DC000h to DFFFFh 3Com 3C509 and 3C509-TP Technical Reference Guide 7-5 10 0000 Disable boot PROM 10 0001 C0000h to C7FFFh 10 01xx C8000h to CFFFFh 10 10xx D0000h to D7FFFh 10 11xx D8000h to DFFFFh 11 0000 Disable boot PROM 11 xxxx Undefined - reserved I/O BASE (I/O base address): 0-30 (0h-1Eh) = Select ISA mode I/O address decode. I/O base address = value (in hexadecimal) * 10h + 200h. 31 (1Fh) = Select EISA mode slot-specific I/O address. I/O base address = x000 (x = slot number). Window 0 also always visible at xC80. 7.4.5 Resource Configuration Register (Read/Write - Offset 8) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | IRQ | F | Reserved | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The automatic configuration logic loads this register. IRQ: Interrupt Request select (values given in decimal). {3,5,7,9,10,11,12,15} = Enable corresponding IRQ line driver. {0,1,2,4,6,8,13,14} = Disable all IRQ line drivers. RES: Reserved 7.4.6 EEPROM Command Register (Read/Write - Offset A) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |EBY|TST| | TAG | EEPROM Command | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ EBY: EEPROM Busy status (read only). 0 = EEPROM not busy. 1 = EEPROM busy. I/O writes to the EEPROM command are disabled. TST: Test Mode (read only). Set at reset time if the EEPROM data input pin is pulled low with external resistor to GND. If set, disables boot PROM. Refer to "Test Mode and Bad Configuration Recovery," later in this chapter. TAG: Tag Register (read only). Set by the ID Sequence State machine. EEPROM Command: Commands written here are shifted out to the on-board EEPROM. There is a 2-bit op code field and a 6-bit address field. For all Erase and Write commands, the hardware times the 10 ms write strobe and then automatically executes the Erase/Write Disable command. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-6 NOTE: The Erase/Write Enable command provides protection from accidental writes to the EEPROM. Software must wait for the EEPROM Busy status bit to go off before writing the next command. Command OP Code Address Data Exe Time ------- ------- ------- ---- -------- Read Register 10 a(5:0) yes 162 us Write Register 01 a(5:0) yes 11 ms Erase Register 11 a(5:0) no 11 ms Erase/Write Enable 00 11xxxx no 60 us Erase/Write Disable 00 00xxxx no 60 us Erase All Registers 00 10xxxx no 11 ms Write All Registers 00 01xxxx yes 11 ms NOTE: The Erase commands write all 1s into the EEPROM. The Write commands write only 0s. To write data into an EEPROM word, you must issue an Erase/Write Enable (EWEN) command, an Erase command, and an EWEN command; load the data into the EEPROM Data register; and issue a Write command. Remember that you must verify that the EEPROM Busy bit (EEPROM Command register bit 15) is off (zero) before writing a command to the EEPROM Command register or data to the EEPROM Data register. 7.4.7 EEPROM Data Register (Read/Write - Offset C) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | EEPROM Data | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ Write data must be written to the EEPROM Data register before the Write command is given to the EEPROM. Read data can be read here after the EEPROM Busy status bit goes off. The configuration and driver software must be careful to leave the Product ID in this register after using the EEPROM. Otherwise, the EISA system configuration software will not be able to identify the adapter after a warm boot. 7.4.8 Command Register (Read/Write - Offset E) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Command | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ The only valid commands in Window 0 are Window commands to select another window. 7.5 Test Mode and "Bad" Configuration Recovery It is the responsibility of the user (with help from the configuration program) to avoid configuring the boot PROM on the adapter in such a way that the system is not able to boot. If this does occur, you can manually jumper Test Via using a #2 pencil. The Test Via forces the adapter into test mode which disables the boot PROM so that the adapter configuration program can be run. You must cover the designated area thoroughly with the pencil. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-7 Test mode forces the adapter not to perform the Automatic Initialization sequence, which means the EEPROM is not read and the adapter is left in the following configuration: - Address Configuration register = 0000h - Resource Configuration register = 0000h - Product ID register = 0000h Test mode also shortens the ID sequence to 8 bytes (first is still FFh and last is 69h) and forces it to the active state (that is, the adapter is active and will respond to I/O cycles at base address 0200h even without going through the ID sequence). After you are done, thoroughly erase the pencil mark. 7.6 EEPROM Data Structure Offset Field Name Default (Hex) ------ ---------- ------------- 00 3Com Node Address (word 0) 0060 01 3Com Node Address (word 1) 8CXX 02 3Com Node Address (word 2) XXXX 03 3C509 Product ID 9X50 04 Manufacturing Data (date)* XXXX 05 Manufacturing Data XXXX 06 Manufacturing Data XXXX 07 Manufacturer Code (6D50h) 6D50 08 Address Configuration XXXX 09 Resource Configuration XXXX 0A OEM Node Address (word 0) 0060 0B OEM Node Address (word 1) 8CXX 0C OEM Node Address (word 2) XXXX 0D Software Information XXXX 0E Reserved XXXX 0F Checksum XXXX 10 to 3F Network Management Data XXXX "X" represents a value that may vary from adapter to adapter. * Manufacturing date format: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ | Year | Month | Day | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ - Year is 0 through 99 and represents the last two digits of the current year. - Month is 1 through 12. - Day is 1 through 31. 3Com 3C509 and 3C509-TP Technical Reference Guide 7-8 Chapter 8 ISA/EISA Bus Interface 8.1 Supported Slot Types and Cycle Types 8.1.1 16-bit ISA Slot The 3C509 adapter supports 8-bit and 16-bit I/O cycles. It supports 8-bit and 16-bit memory read cycles as an 8-bit adapter (does not assert MEMCS16). It only supports default timing (does not assert 0WS or de-assert IOCHRDY) as specified in the technical reference guide for the IBM (R) Personal Computer AT (R). 8.1.2 EISA Slot The 3C509 adapter supports 8-bit and 16-bit I/O cycles. It supports 8-bit and 16-bit memory read cycles as an 8-bit ISA adapter. It only supports default timing as specified in the EISA specification, version 3.10, section 2.11.4.1 ISA-compatible Timing Parameters. 8.2 DC Characteristics - Pin Drive/Load Types Type 3SH 3SL OC BI IN IN2 Units ---- --- --- -- -- -- --- ----- Voh 2.4 2.4 - 2.4 min Volts Vol 0.4 0.4 0.4 0.4 max Volts Ioh 3.0 0.4 - 3.0 max mAmps Iol 24.0 5.0 24.0 24.0 max mAmps Vih 2.0 2.0 2.0 min Volts Vil 0.8 0.8 0.8 max Volts Iih 10.0 10.0 20.0 max uAmps Iil 10.0 10.0 20.0 max uAmps Icap 15 15 15 15 15 15 max pF 8.3 Board Edge Connector Pins Pin No. Pin Name Description Type Notes ------- -------- ----------- ---- ----- A2-9 SD7-0 Low byte data bus BI A11 AEN Address enable IN A12-15 SA19-16 Latched address bus I A16-31 SA15-0 Latched address bus IN2 2 B2 RESETDRV Power-on reset IN B4 IRQ9 Interrupt request 9 3SH 1 B12 SMEMR- Memory read strobe IN B13 IOW- I/O write strobe IN B14 IOR- I/O read strobe IN B21 IRQ7 Interrupt request 7 3SH 1 B23 IRQ5 Interrupt request 5 3SH 1 B25 IRQ3 Interrupt request 3 3SH 1 B27 T/C Not Used IN C1 SBHE- High-byte enable IN C11-18 SD8-15 High-byte data bus BI 3Com 3C509 and 3C509-TP Technical Reference Guide 8-1 D2 IOCS16- 16-bit I/O select OC D3 IRQ10 Interrupt request 10 3SH 1 D4 IRQ11 Interrupt request 11 3SH 1 D5 IRQ12 Interrupt request 12 3SH 1 D6 IRQ15 Interrupt request 15 3SH 1 D10 DACK5- Not Used IN D11 DRQ5 Not Used 3SH D12 DACK6- Not Used IN D13 DRQ6 Not Used 3SH D14 DACK7- Not Used IN D15 DRQ7 Not Used 3SH B1,B10,B31,D18 GND B3,B29,D16 +5 volts @ .4 amp max. 3 B9 +12 volts @ .5 amp max. 4 NOTES: 1. Although both the IBM technical reference guide and the EISA specification specify an open collector driver on the IRQ signals, you cannot assume there will be a reasonable pullup resistor on these lines in all ISA machines. The 3C509 adapter will use tri-state drivers on these lines and drive the selected IRQ signal high (similar to 3Com's EtherLink (R) 16 adapter). This means that the 3C509 adapter does not support shared interrupts. 2. SA15-0 are the only bus interface signals that go to more than one IC pin on the 3C509 adapter. They are connected to both the 3C509 ASIC and the boot PROM address pins. 3. Max +5V current 150 mAmps 4. Max +12V current standby 0 mAmps 10BASE-T transceiver on 0 mAmps 10BASE2 transceiver on 300 mAmps External transceiver on 500 mAmps 3Com 3C509 and 3C509-TP Technical Reference Guide 8-2 Chapter 9 External Configuration Options The 3C509 ASIC supports a wide variety of external configuration options. These options are available to support board-level testing and notify the ASIC and the host software of media resource support. 9.1 Boundary Scan Configuration When the ResetPinIn is asserted, a boundary scan ring is given access to the ASIC's I/O pins. RData[7:4] acts as the control port to the boundary scan with the following functionality: Bit Function I/O --- -------- --- RData[7] DataIn Input RData[6] DataOut Output RData[5] BClk Input RData[4] Shift/!Load Input Listed below are the I/O pins available to boundary scan and their functionality with respect to the ASIC. Inputs Outputs ------ ------- SBHE_ DRQ[7:5] AENA EEDataO IOR_ EEClockO IOW_ IOCS16_ SMRD_ LEDDrvO_ SAIn[19:0] IRQ[15, 12:9, 7, 5, 3] EEPROMDIn SData[15:0] 9.2 Forced Configuration The EEPROMDIn pin is sampled at the falling edge of ResetPinIn. The ASIC is configured with an I/O base address of 200h, the boot PROM is disabled, and the internal 10BASE-T transceiver enabled (independently of the availability of this resource). This option is exercised at board-level test, and can be used in extreme cases by customers if the 3C509 ASIC is incorrectly configured in a machine. 9.3 Physical Layer Configuration RData[5:0] are used to notify the 3C509 ASIC of its external physical layer resources. As with forced configuration, these pins are sampled on the falling edge of ResetPinIn, and various configurations are strapped via pulldown resistors on the PC board. NOTE: These configurations must not be modified by the end user. 3Com 3C509 and 3C509-TP Technical Reference Guide 9-1 Physical layer resources are encoded as follows: RData Resources Available ----- ------------------- 0 Internal encoder/decoder 1 10BASE-T transceiver (through internal interface) 2 See "Physical Layer Test Access" (below) 3 See "Physical Layer Test Access" (below) 4 10BASE2 transceiver (through AUI and DC-DC converter) 5 15-pin AUI connector Except for the external encoder/decoder configuration, an internal AUI transceiver is available in all configurations. NOTE: The external encoder/decoder configuration is for testing purposes only. 9.4 Physical Layer Test Access RData[3:2] (as sampled at the falling edge of ResetPinIn) allow access to the physical layer for test purposes. The various access ports are windowed to the RData[7:0] bus, and are listed below. Pin 3 Pin 2 Mode ----- ----- ---- 0 0 Reserved 0 1 Receive Physical Access 1 0 Transmit Physical Access 1 1 Normal EEPROM Access (Default) 3Com 3C509 and 3C509-TP Technical Reference Guide 9-2